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adc10061 , adc10062 , adc10064 www.ti.com snas069e ? june 1999 ? revised march 2013 adc10061/adc10062/adc10064 10-bit 600 ns a/d converter with input multiplexer and sample/hold check for samples: adc10061 , adc10062 , adc10064 1 features description note: the adc10061 and adc10062 are obsolete. 2 ? built-in sample-and-hold they are described here for reference only. ? single +5v supply using an innovative, patented multistep* conversion ? no external clock required technique, these cmos analog-to-digital converters ? speed adjust pin for faster conversions offer sub-microsecond conversion times yet dissipate (adc10062 and adc10064). see adc10662/4 a maximum of only 235 mw. these converters for high speed ensured performance. perform 10-bit conversions in two lower-resolution ? flashes ? , yielding a fast a/d without the cost, power applications consumption, and other problems associated with true flash approaches. ? digital signal processor front ends the analog input voltage is sampled and held by an ? instrumentation internal sampling circuit. input signals at frequencies ? disk drives from dc to over 200 khz can, therefore, be digitized ? mobile telecommunications accurately without the need for an external sample- and-hold circuit. key specifications the adc10062 and adc10064 include a ? speed-up ? ? conversion time 600 ns typical, 900 ns max pin. connecting an external resistor between this pin and ground reduces the typical conversion time to as ? sampling rate 800 khz little as 350 ns with only a small increase in linearity ? low power dissipation 235 mw (max) error. ? total unadjusted error 1.0 lsb (max) for ease of interface to microprocessors, the ? no missing codes over temperature adc10061, adc10062, and adc10064 have been designed to appear as a memory location or i/o port without the need for external interface logic. *u.s. patent number 4918449 simplified block diagram *adc10061 only, **adc10062 and adc10064 only, ***adc10064 only 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 all trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 1999 ? 2013, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
adc10061 , adc10062 , adc10064 snas069e ? june 1999 ? revised march 2013 www.ti.com connection diagram this device is obsolete; shown for reference only. figure 1. top view this device is obsolete; shown for reference only. figure 2. top view figure 3. top view 2 submit documentation feedback copyright ? 1999 ? 2013, texas instruments incorporated product folder links: adc10061 adc10062 adc10064
adc10061 , adc10062 , adc10064 www.ti.com snas069e ? june 1999 ? revised march 2013 note: the adc10061 and adc10062 are obsolete; shown for reference only. pin descriptions pin function description dv cc , av cc digital and analog positive supply voltage inputs. connect both to the same voltage source, but bypass separately with a 0.1 f ceramic capacitor in parallel with a 10 f tantalum capacitor to ground at each pin. int active low interrupt output. int goes low at the end of each conversion, and returns high following the rising edge of rd. s/h sample/hold control input. when this pin is forced low (and cs is low), the analog input signal is sampled and a new conversion is initiated. rd active low read control input. when this rd and cs are low, any data present in the output registers will be placed onto the data bus. cs active low chip select control input. when low, this pin enables the rd and s/h pins. s0, s1 on the multiple-input devices (adc10062 and adc10064), these pins select the analog input that will be connected to the a/d during the conversion. the input is selected based on the state of s0 and s1 when s/h makes its high-to-low transition (see timing diagrams ). the adc10064 includes both s0 and s1. the adc10062 includes just s0, and the adc10061 has neither. v ref ? , v ref+ reference voltage inputs. they may be placed at any voltage between gnd and v cc , but v ref+ must be greater than v ref ? . an input voltage equal to v ref ? produces an output code of 0, and an input voltage equal to (v ref+ ? 1 lsb) produces an output code of 1023. v in , v in0 , v in1 , analog input pins. the adc10061 has one input (v in ), the adc10062 has two inputs (v in0 and v in1 ), and the v in2 , v in3 adc10064 has four inputs (v in0 , v in1 , v in2 and v in3 ). the impedance of the input source should be less than 500 for best accuracy and conversion speed. for accurate conversions, no input pin (even one that is not selected) should be driven more than 50 mv above v cc or 50 mv below ground. gnd, agnd, power supply ground pins. the adc10061 has a single ground pin (gnd), and the adc10062 and adc10064 have dgnd separate analog and digital ground pins (agnd and dgnd) for separate bypassing of the analog and digital supplies. the ground pins should be connected to a stable, noise-free system ground. for the devices with two ground pins, both pins should be returned to the same potential. db0 ? db9 tri-state data output pins. speed adj (adc10062 and adc10064 only). this pin is normally left unconnected, but by connecting a resistor between this pin and ground, the conversion time can be reduced. see typical performance characteristics and the table of electrical characteristics. these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. copyright ? 1999 ? 2013, texas instruments incorporated submit documentation feedback 3 product folder links: adc10061 adc10062 adc10064
adc10061 , adc10062 , adc10064 snas069e ? june 1999 ? revised march 2013 www.ti.com absolute maximum ratings (1) (2) (3) supply voltage (v + = av cc = dv cc ) ? 0.3v to +6v voltage at any input or output ? 0.3v to v + + 0.3v input current at any pin (4) 5 ma package input current (4) 20 ma power consumption (5) 875 mw esd susceptibility (6) 2000v vapor phase (60 sec) 215 c soldering information infrared (15 sec) 220 c storage temperature range ? 65 c to +150 c junction temperature 150 c (1) absolute maximum ratings indicate limits beyond which damage to the device may occur. operating ratings indicate conditions for which the device is functional. these ratings do not ensure specific performance limits, however. for ensured specifications and test conditions, see the electrical characteristics. the ensured specifications apply only for the test conditions listed. some performance characteristics may degrade when the device is not operated under the listed test conditions. (2) all voltages are measured with respect to gnd, unless otherwise specified. (3) if military/aerospace specified devices are required, please contact the texas instruments sales office/distributors for availability and specifications. (4) when the input voltage (v in ) at any pin exceeds the power supply rails (v in < gnd or v in > v + ) the absolute value of current at that pin should be limited to 5 ma or less. the 20 ma package input current limits the number of pins that can safely exceed the power supplies with an input current of 5 ma to four. (5) the maximum power dissipation must be derated at elevated temperatures and is dictated by t jmax , ja and the ambient temperature, t a . the maximum allowable power dissipation at any temperature is p d = (t jmax ? t a )/ ja or the number given in the absolute maximum ratings, whichever is lower. in most cases, the maximum derated power dissipation will be reached only during fault conditions. for these devices, t jmax for a board-mounted device are as indicated in package thermal resistance . (6) human body model, 100 pf discharged through a 1.5 k resistor. operating ratings (1) (2) t min t a t max = temperature range ? 40 c t a +85 c supply voltage range +4.5v to +5.5v (1) absolute maximum ratings indicate limits beyond which damage to the device may occur. operating ratings indicate conditions for which the device is functional. these ratings do not ensure specific performance limits, however. for ensured specifications and test conditions, see the electrical characteristics. the ensured specifications apply only for the test conditions listed. some performance characteristics may degrade when the device is not operated under the listed test conditions. (2) all voltages are measured with respect to gnd, unless otherwise specified. package thermal resistance device ja ( c/w) adc10061ciwm 85 adc10062ciwm 82 adc10064ciwm 78 converter characteristics the following specifications apply for v + = +5v, v ref(+) = +5v, v ref( ? ) = gnd, and speed adjust pin unconnected unless otherwise specified. boldface limits apply for t a = t j = t min to t max ; all other limits t a = t j = +25 c. units symbol parameter conditions typical (1) limit (2) (limit) resolution 10 bits integral linearity error r sa = 18 k 0.5 1.0/ 1.5 lsb (max) offset error 1.5 lsb (max) full-scale error 1 lsb (max) total unadjusted error all suffixes, r sa = 18 k 0.5 1.5/ 2.2 lsb (max) missing codes] 0 (max) (1) typical numbers are at +25 c and represent must likely parametric norm. (2) limits are specified to ti ' s aoql (average outgoing quality level). 4 submit documentation feedback copyright ? 1999 ? 2013, texas instruments incorporated product folder links: adc10061 adc10062 adc10064
adc10061 , adc10062 , adc10064 www.ti.com snas069e ? june 1999 ? revised march 2013 converter characteristics (continued) the following specifications apply for v + = +5v, v ref(+) = +5v, v ref( ? ) = gnd, and speed adjust pin unconnected unless otherwise specified. boldface limits apply for t a = t j = t min to t max ; all other limits t a = t j = +25 c. units symbol parameter conditions typical (1) limit (2) (limit) v + = 5v 5%, v ref = 4.5v 1/16 lsb power supply sensitivity v + = 5v 10%, v ref = 4.5v ? lsb (max) f in = 10 khz, 4.85 v p-p 0.06 % thd total harmonic distortion f in = 160 khz, 4.85 v p-p 0.08 % f in = 10 khz, 4.85 v p-p 61 db snr signal-to-noise ratio f in = 160 khz, 4.85 v p-p 60 db f in = 10 khz, 4.85 v p-p 9.6 bits effective number of bits f in = 160 khz, 4.85 v p-p 9.4 bits r ref reference resistance 650 400 (min) r ref reference resistance 650 900 (max) v ref(+) v ref(+) input voltage v + + 0.05 v (max) v ref( ? ) v ref( ? ) input voltage gnd ? 0.05 v (min) v ref(+) v ref(+) input voltage v ref( ? ) v (min) v ref( ? ) v ref( ? ) input voltage v ref(+) v (max) v in input voltage v + + 0.05 v (max) v in input voltage gnd ? 0.05 v (min) off channel input leakage current cs = v + , v in = v + 0.01 3 a (max) on channel input leakage current cs = v + , v in = v + 1 ? 3 a (max) dc electrical characteristics the following specifications apply for v + = +5v, v ref(+) = 5v v ref( ? ) = gnd, and speed adjust pin unconnected unless otherwise specified. boldface limits apply for t a = t j = t min to t max ; all other limits t a = t j = +25 c. units symbol parameter conditions typical (1) limit (2) (limit) v in(1) logical ? 1 ? input voltage v + = 5.5v 2.0 v (min) v in(0) logical ? 0 ? input voltage v + = 4.5v 0.8 v (max) i in(1) logical ? 1 ? input current v in(1) = 5v 0.005 3.0 a (max) i in(0) logical ? 0 ? input current v in(0) 0v ? 0.005 ? 3.0 a (max) v + = 4.5v, i out = ? 360 a 2.4 v (min) v out(1) logical ? 1 ? output voltage v + = 4.5v, i out = ? 10 a 4.25 v (min) v out(0) logical ? 0 ? output voltage v + = 4.5v, i out = 1.6 ma 0.4 v (max) v out = 5v 0.1 50 a (max) i out tri-state output current v out = 0v ? 0.1 ? 50 a (max) cs = s/h = rd = 0, r sa = 1.0 2 ma (max) di cc dv cc supply current cs = s/h = rd = 0, r sa = 18 k ? 1.0 2 ma (max) cs = s/h = rd = 0, r sa = 30 45 ma (max) ai cc av cc supply current cs = s/h = rd = 0, r sa = 18 k ? 30 45 ma (max) (1) typical numbers are at +25 c and represent must likely parametric norm. (2) limits are specified to ti ' s aoql (average outgoing quality level). ac electrical characteristics the following specifications apply for v + = +5v, t r = t f = 20 ns, v ref(+) = 5v, v ref( ? ) = gnd, and speed adjust pin unconnected unless otherwise specified. boldface limits apply for t a = t j = t min to t max ; all other limits t a = t j = +25 c. units symbol parameter conditions typical (1) limit (2) (limit) mode 1 conversion time from rising r sa = 600 750/ 900 ns (max) t conv edge of s/h to falling edge of int r sa = 18k 375 ns (1) typical numbers are at +25 c and represent must likely parametric norm. (2) limits are specified to ti ' s aoql (average outgoing quality level). copyright ? 1999 ? 2013, texas instruments incorporated submit documentation feedback 5 product folder links: adc10061 adc10062 adc10064
adc10061 , adc10062 , adc10064 snas069e ? june 1999 ? revised march 2013 www.ti.com ac electrical characteristics (continued) the following specifications apply for v + = +5v, t r = t f = 20 ns, v ref(+) = 5v, v ref( ? ) = gnd, and speed adjust pin unconnected unless otherwise specified. boldface limits apply for t a = t j = t min to t max ; all other limits t a = t j = +25 c. units symbol parameter conditions typical (1) limit (2) (limit) r sa = 850 1400 ns (max) t crd mode 2 conversion time mode 2, r sa = 18k 530 ns access time (delay from falling edge of t acc1 mode 1; c l = 100 pf 30 60 ns (max) rd to output valid) access time (delay from falling edge of t acc2 mode 2; c l = 100 pf 900 t crd + 50 ns (max) rd to output valid) t sh minimum sample time (3) figure 4 (2) 250 ns (max) tri-state control (delay from rising t 1h , t 0h r l = 1k, c l = 10 pf 30 60 ns (max) edge of rd to high-z state) delay from rising edge of rd to rising t inth c l = 100 pf 25 50 ns (max) edge of int delay from end of conversion to next t p 50 ns (max) conversion t ms multiplexer control setup time 10 75 ns (max) t mh multiplexer hold time 10 40 ns (max) c vin analog input capacitance 35 pf (max) c out logic output capacitance 5 pf (max) c in logic input capacitance 5 pf (max) (3) accuracy may degrade if t sh is shorter than the value specified. see curves of accuracy vs. t sh . tri-state test circuits and waveforms 6 submit documentation feedback copyright ? 1999 ? 2013, texas instruments incorporated product folder links: adc10061 adc10062 adc10064
adc10061 , adc10062 , adc10064 www.ti.com snas069e ? june 1999 ? revised march 2013 timing diagrams the conversion time (t conv ) is set by the internal timer. figure 4. mode 1 the conversion time (t crd ) includes the sampling time and is determined by the internal timer. figure 5. mode 2 ( rd mode) copyright ? 1999 ? 2013, texas instruments incorporated submit documentation feedback 7 product folder links: adc10061 adc10062 adc10064
adc10061 , adc10062 , adc10064 snas069e ? june 1999 ? revised march 2013 www.ti.com typical performance characteristics zero (offset) error linearity error vs. reference voltage vs. reference voltage figure 6. figure 7. analog supply current digital supply current vs. temperature vs. temperature figure 8. figure 9. conversion time conversion time vs. temperature vs. temperature figure 10. figure 11. 8 submit documentation feedback copyright ? 1999 ? 2013, texas instruments incorporated product folder links: adc10061 adc10062 adc10064
adc10061 , adc10062 , adc10064 www.ti.com snas069e ? june 1999 ? revised march 2013 typical performance characteristics (continued) conversion time conversion time vs. speed-up resistor vs. speed-up resistor (adc10062 and adc10064 only) (adc10062 and adc10064 only) figure 12. figure 13. spectral response with100 khz sine spectral response with wave input 100 khz sine wave input figure 14. figure 15. linearity change signal-to-noise + thd ratio vs. speed-up resistor vs. signal frequency (adc10062 and adc10064 only) figure 16. figure 17. copyright ? 1999 ? 2013, texas instruments incorporated submit documentation feedback 9 product folder links: adc10061 adc10062 adc10064
adc10061 , adc10062 , adc10064 snas069e ? june 1999 ? revised march 2013 www.ti.com typical performance characteristics (continued) linearity change vs. speed-up resistor linearity error change (adc10062 and adc10064 only) vs. sample time figure 18. figure 19. functional description the adc10061 and the adc10062 are obsolete. they are discussed here for reference only. the adc10061, adc10062 and adc10064 digitize an analog input signal to 10 bits accuracy by performing two lower-resolution ? flash ? conversions. the first flash conversion provides the six most significant bits (msbs) of data, and the second flash conversion provides the four least significant bits lsbs). figure 20 is a simplified block diagram of the converter. near the center of the diagram is a string of resistors. at the bottom of the string of resistors are 16 resistors, each of which has a value 1/1024 the resistance of the whole resistor string. these lower 16 resistors (the lsb ladder ) therefore have a voltage drop of 16/1024, or 1/64 of the total reference voltage (v ref+ ? v ref ? ) across them. the remainder of the resistor string is made up of eight groups of eight resistors connected in series. these comprise the msb ladder . each section of the msb ladder has ? of the total reference voltage across it, and each of the lsb resistors has 1/64 of the total reference voltage across it. tap points across these resistors can be connected, in groups of sixteen, to the sixteen comparators at the right of the diagram. on the left side of the diagram is a string of seven resistors connected between v ref+ and v ref ? . six comparators compare the input voltage with the tap voltages on this resistor string to provide a low-resolution ? estimate ? of the input voltage. this estimate is then used to control the multiplexer that connects the msb ladder to the sixteen comparators on the right. note that the comparators on the left needn't be very accurate; they simply provide an estimate of the input voltage. only the sixteen comparators on the right and the six on the left are necessary to perform the initial six-bit flash conversion, instead of the 64 comparators that would be required using conventional half-flash methods. to perform a conversion, the estimator compares the input voltage with the tap voltages on the seven resistors on the left. the estimator decoder then determines which msb ladder tap points will be connected to the sixteen comparators on the right. for example, assume that the estimator determines that v in is between 11/16 and 13/16 of v ref . the estimator decoder will instruct the comparator mux to connect the 16 comparators to the taps on the msb ladder between 10/16 and 14/16 of v ref . the 16 comparators will then perform the first flash conversion. note that since the comparators are connected to ladder voltages that extend beyond the range indicated by the estimator circuit, errors in the estimator as large as 1/16 of the reference voltage (64 lsbs) will be corrected. this first flash conversion produces the six most significant bits of data ? four bits in the flash itself, and 2 bits in the estimator. the remaining four lsbs are now determined using the same sixteen comparators that were used for the first flash conversion. the msb ladder tap voltage just below the input voltage (as determined by the first flash) is subtracted from the input voltage and compared with the tap points on the sixteen lsb ladder resistors. the result of this second, four-bit flash conversion is then decoded, and the full 10-bit result is latched. 10 submit documentation feedback copyright ? 1999 ? 2013, texas instruments incorporated product folder links: adc10061 adc10062 adc10064
adc10061 , adc10062 , adc10064 www.ti.com snas069e ? june 1999 ? revised march 2013 note that the sixteen comparators used in the first flash conversion are reused for the second flash. thus, the multistep conversion technique used in the adc10061, adc10062, and adc10064 needs only a small fraction of the number of comparators that would be required for a traditional flash converter, and far fewer than would be used in a conventional half-flash approach. this allows the adc10061, adc10062, and adc10064 to perform high-speed conversions without excessive power drain. figure 20. block diagram of the multistep converter architecture similar product differences the adc1006x, adc1046x and adc1066x (where "x" indicates the number of multiplexer inputs) are similar devices with different specification limits. the differences in these device families are summarized below. device family ile, tue, pss thd, snr, enob max. conversion time adc1006x ensured - 900ns adc1046x - ensured 900ns adc1066x - ensured 466ns copyright ? 1999 ? 2013, texas instruments incorporated submit documentation feedback 11 product folder links: adc10061 adc10062 adc10064
adc10061 , adc10062 , adc10064 snas069e ? june 1999 ? revised march 2013 www.ti.com applications information modes of operation the adc10061, adc10062, and adc10064 have two basic digital interface modes. figure 4 and figure 5 are timing diagrams for the two modes. the adc10062 and adc10064 have input multiplexers that are controlled by the logic levels on pins s 0 and s 1 when s/h goes low. table 1 is a truth table showing how the input channels are assigned. mode 1 in this mode, the s/h pin controls the start of conversion. s/h is pulled low for a minimum of 250 ns. this causes the comparators in the ? coarse ? flash converter to become active. when s/h goes high, the result of the coarse conversion is latched and the ? fine ? conversion begins. after 600 ns (typical), int goes low, indicating that the conversion results are latched and can be read by pulling rd low. note that cs must be low to enable s/h or rd. cs is internally ? anded ? with s/h and rd; the input voltage is sampled when cs and s/h are low, and data is read when cs and rd are low. int is reset high on the rising edge of rd. table 1. input multiplexer programming adc10064 (a) s 1 s 0 channel 0 0 v in0 0 1 v in1 1 0 v in2 1 1 v in3 adc10062 (b) s 0 channel 0 v in0 1 v in1 mode 2 in mode 2, also called ? rd mode ? , the s/h and rd pins are tied together. a conversion is initiated by pulling both pins low. the a/d converter samples the input voltage and causes the coarse comparators to become active. an internal timer then terminates the coarse conversion and begins the fine conversion. 850 ns (typical) after s/h and rd are pull low, int goes low, indicating that the conversion is completed. approximately 20 ns later the data appearing on the tri-state output pins will be valid. note that data will appear on these pins throughout the conversion, but until int goes low the data at the output pins will be the result of the previous conversion. reference considerations the adc10061, adc10062, and adc10064 each have two reference inputs. these inputs, v ref+ and v ref ? , are fully differential and define the zero to full-scale range of the input signal. the reference inputs can be connected to span the entire supply voltage range (v ref ? = 0v, v ref+ = v cc ) for ratiometric applications, or they can be connected to different voltages (as long as they are between ground and v cc ) when other input spans are required. reducing the overall v ref span to less than 5v increases the sensitivity of the converter (e.g., if v ref = 2v, then 1 lsb = 1.953 mv). note, however, that linearity and offset errors become larger when lower reference voltages are used. see typical performance characteristics for more information. for this reason, reference voltages less than 2v are not recommended. in most applications, v ref ? will simply be connected to ground, but it is often useful to have an input span that is offset from ground. this situation is easily accommodated by the reference configuration used in the adc10061, adc10062, and adc10064. v ref ? can be connected to a voltage other than ground as long as the voltage source connected to this pin is capable of sinking the converter's reference current (12.5 ma max @ v ref = 5v). if v ref ? is connected to a voltage other than ground, bypass it with multiple capacitors. 12 submit documentation feedback copyright ? 1999 ? 2013, texas instruments incorporated product folder links: adc10061 adc10062 adc10064
adc10061 , adc10062 , adc10064 www.ti.com snas069e ? june 1999 ? revised march 2013 since the resistance between the two reference inputs can be as low as 400 , the voltage source driving the reference inputs should have low output impedance. any noise on either reference input is a potential cause of conversion errors, so each of these pins must be supplied with a clean, low noise voltage source. each reference pin should be bypassed with a 10 f tantalum and a 0.1 f ceramic. the analog input the adc10061, adc10062, and adc10064 sample the analog input voltage once every conversion cycle. when this happens, the input is briefly connected to an impedance approximately equal to 600 in series with 35 pf. short-duration current spikes can be observed at the analog input during normal operation. these spikes are normal and do not degrade the converter's performance. large source impedances can slow the charging of the sampling capacitors and degrade conversion accuracy. therefore, only signal sources with output impedances less than 500 should be used if rated accuracy is to be achieved at the minimum sample time (250 ns maximum). if the sampling time is increased, the source impedance can be larger. if a signal source has a high output impedance, its output should be buffered with an operational amplifier. the operational amplifier's output should be well-behaved when driving a switched 35 pf/600 load. any ringing or voltage shifts at the op-amp's output during the sampling period can result in conversion errors. correct conversion results will be obtained for input voltages greater than gnd ? 50 mv and less than v + + 50 mv. do not allow the signal source to drive the analog input pin beyond the absolute maximum rating. if an analog input pin is forced beyond these voltages, the current flowing through the pin should be limited to 5 ma or less to avoid permanent damage to the ic. the sum of all the overdrive currents into all pins must be less than the absolute maximum rating for package input current. when the input signal is expected to extend beyond this limit, an input protection scheme should be used. a simple input protection network using diodes and resistors is shown in figure 21 . note the multiple bypass capacitors on the reference and power supply pins. if v ref ? is not grounded, it should also be bypassed to analog ground using multiple capacitors (see power supply considerations ). agnd and dgnd should be at the same potential. v in0 is shown with an input protection network. pin 17 is normally left open, but optional ? speedup ? resistor r sa can be used to reduce the conversion time. figure 21. typical connection inherent sample-and-hold because the adc10061, adc10062, and adc10064 sample the input signal once during each conversion, they are capable of measuring relatively fast input signals without the help of an external sample-hold. in a non- sampling successive-approximation a/d converter, regardless of speed, the input signal must be stable to better than 1/2 lsb during each conversion cycle or significant errors will result. consequently, even for many relatively slow input signals, the signals must be externally sampled and held constant during each conversion if a sar with no internal sample-and-hold is used. copyright ? 1999 ? 2013, texas instruments incorporated submit documentation feedback 13 product folder links: adc10061 adc10062 adc10064
adc10061 , adc10062 , adc10064 snas069e ? june 1999 ? revised march 2013 www.ti.com because they incorporate a direct sample/hold control input, the adc10061, adc10062, and adc10064 are suitable for use in dsp-based systems. the s/h input allows synchronization of the a/d converter to the dsp system's sampling rate and to other adc10061s, adc10062s, and adc10064s. power supply considerations the adc10061, adc10062, and adc10064 are designed to operate from a +5v (nominal) power supply. there are two supply pins, av cc and dv cc . these pins allow separate external bypass capacitors for the analog and digital portions of the circuit. to ensure accurate conversions, the two supply pins should be connected to the same voltage source, and each should be bypassed with a 0.1 f ceramic capacitor in parallel with a 10 f tantalum capacitor. depending upon the circuit board layout and other system considerations, more bypassing may be necessary. the adc10061 has a single ground pin, and the adc10062 and adc10064 each have separate analog and digital ground pins for separate bypassing of the analog and digital supplies. the devices with separate analog and digital ground pins should have their ground pins connected to the same potential, and all grounds should be ? clean ? and free of noise. in systems with multiple power supplies, careful attention to power supply sequencing may be necessary to avoid over-driving inputs. the a/d converter's power supply pins should be at the proper voltage before digital or analog signals are applied to any of the other pins. layout and grounding in order to ensure fast, accurate conversions from the adc10061, adc10062, and adc10064, it is necessary to use appropriate circuit board layout techniques. the analog ground return path should be low-impedance and free of noise from other parts of the system. noise from digital circuitry can be especially troublesome. all bypass capacitors should be located as close to the converter as possible and should connect to the converter and to ground with short traces. the analog input should be isolated from noisy signal traces to avoid having spurious signals couple to the input. any external component (e.g., a filter capacitor) connected across the converter's input should be connected to a very clean ground return point. grounding the component at the wrong point will result in reduced conversion accuracy. dynamic performance many applications require the a/d converter to digitize ac signals, but conventional dc integral and differential nonlinearity specifications don't accurately predict the a/d converter's performance with ac input signals. the important specifications for ac applications reflect the converter's ability to digitize ac signals without significant spectral errors and without adding noise to the digitized signal. dynamic characteristics such as signal-to-noise ratio (snr) and total harmonic distortion (thd), are quantitative measures of this capability. an a/d converter's ac performance can be measured using fast fourier transform (fft) methods. a sinusoidal waveform is applied to the a/d converter's input, and the transform is then performed on the digitized waveform. the resulting spectral plot might look like the ones shown in typical performance characteristics . the large peak is the fundamental frequency, and the noise and distortion components (if any are present) are visible above and below the fundamental frequency. harmonic distortion components appear at whole multiples of the input frequency. their amplitudes are combined as the square root of the sum of the squares and compared to the fundamental amplitude to yield the thd specification. typical values for thd are given in the table of electrical characteristics. signal-to-noise ratio is the ratio of the amplitude at the fundamental frequency to the rms value at all other frequencies, excluding any harmonic distortion components. typical values are given in the electrical characteristics table. an alternative definition of signal-to-noise ratio includes the distortion components along with the random noise to yield a signal-to-noise-plus-distortion ratio, or s/(n + d). the thd and noise performance of the a/d converter will change with the frequency of the input signal, with more distortion and noise occurring at higher signal frequencies. one way of describing the a/d's performance as a function of signal frequency is to make a plot of ? effective bits ? versus frequency. an ideal a/d converter with no linearity errors or self-generated noise will have a signal-to-noise ratio equal to (6.02n + 1.76) db, where n is the resolution in bits of the a/d converter. a real a/d converter will have some amount of noise and distortion, and the effective bits can be found by: 14 submit documentation feedback copyright ? 1999 ? 2013, texas instruments incorporated product folder links: adc10061 adc10062 adc10064
adc10061 , adc10062 , adc10064 www.ti.com snas069e ? june 1999 ? revised march 2013 where ? s/(n + d) is the ratio of signal to noise and distortion, which can vary with frequency (1) as an example, an adc10061 with a 5 v p-p , 100 khz sine wave input signal will typically have a signal-to-noise- plus-distortion ratio of 59.2 db, which is equivalent to 9.54 effective bits. as the input frequency increases, noise and distortion gradually increase, yielding a plot of effective bits or s/(n + d) as shown in typical performance characteristics . speed adjust in applications that require faster conversion times, the speed adjust pin (pin 14 on the adc10062, pin 17 on the adc10064) can significantly reduce the conversion time. the speed adjust pin is connected to an on-chip current source that determines the converter's internal timing. by connecting a resistor between the speed adjust pin and ground as shown in figure 21 , the internal programming current is increased, which reduces the conversion time. as an example, an 18k resistor reduces the conversion time of a typical part from 600 ns to 350 ns with no significant effect on linearity. using smaller resistors to further decrease the conversion time is possible as well, although the linearity will begin to degrade somewhat (see typical performance characteristics ). note that the resistor value needed to obtain a given conversion time will vary from part to part, so this technique will generally require some ? tweaking ? to obtain satisfactory results. copyright ? 1999 ? 2013, texas instruments incorporated submit documentation feedback 15 product folder links: adc10061 adc10062 adc10064
adc10061 , adc10062 , adc10064 snas069e ? june 1999 ? revised march 2013 www.ti.com revision history changes from revision d (march 2013) to revision e page ? changed layout of national data sheet to ti format .......................................................................................................... 15 16 submit documentation feedback copyright ? 1999 ? 2013, texas instruments incorporated product folder links: adc10061 adc10062 adc10064
package option addendum www.ti.com 28-jul-2016 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples adc10064ciwm lifebuy soic dw 28 26 tbd call ti call ti -40 to 85 adc10064 ciwm adc10064ciwm/nopb lifebuy soic dw 28 26 green (rohs & no sb/br) cu sn level-2-260c-1 year -40 to 85 adc10064 ciwm adc10064ciwm/ugn8 lifebuy soic dw 28 tbd call ti call ti adc10064 ciwm adc10064ciwmx/nopb lifebuy soic dw 28 1000 green (rohs & no sb/br) cu sn level-3-260c-168 hr -40 to 85 adc10064 ciwm (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width.
package option addendum www.ti.com 28-jul-2016 addendum-page 2 important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant adc10064ciwmx/nopb soic dw 28 1000 330.0 24.4 10.8 18.4 3.2 12.0 24.0 q1 package materials information www.ti.com 29-apr-2014 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) adc10064ciwmx/nopb soic dw 28 1000 367.0 367.0 45.0 package materials information www.ti.com 29-apr-2014 pack materials-page 2

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